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• Title Page
• Copyright Page
• Preface
• Contents
• Chapter 1 Introductory Concepts
• 1-1 Introduction to Digital 1s and 0s
• 1-2 Digital Signals
• Need for Timing
• Highs and Lows Over Time
• Periodic/Aperiodic
• Period/Frequency
• Duty Cycle
• Transitions
• Edges/Events
• 1-3 Logic Circuits and Evolving Technology
• Logic Circuits
• Digital Integrated Circuits
• 1-4 Numerical Representations
• Analog Representations
• Digital Representations
• 1-5 Digital and Analog Systems
• Advantages of Digital Techniques
• Limitations of Digital Techniques
• 1-6 Digital Number Systems
• Decimal System
• Decimal Counting
• Binary System
• Binary Counting
• 1-7 Representing Signals with Numeric Quantities
• 1-8 Parallel and Serial Transmission
• 1-9 Memory
• 1-10 Digital Computers
• Major Parts of a Computer
• Types of Computers
• Memory
• Digital Progress Today and Tomorrow
• Chapter 2 Number Systems and Codes
• 2-1 Binary-to-Decimal Conversions
• 2-2 Decimal-to-Binary Conversions
• Counting Range
• 2-3 Hexadecimal Number System
• Hex-to-Decimal Conversion
• Decimal-to-Hex Conversion
• Hex-to-Binary Conversion
• Binary-to-Hex Conversion
• Counting in Hexadecimal
• Usefulness of Hex
• Summary of Conversions
• 2-4 BCD Code
• Binary-Coded-Decimal Code
• Comparison of BCD and Binary
• 2-5 The Gray Code
• Quadrature Encoders
• 2-6 Putting it All Together
• 2-7 The Byte, Nibble, and Word
• Bytes
• Nibbles
• Words
• 2-8 Alphanumeric Codes
• ASCII Code
• 2-9 Parity Method For Error Detection
• Parity Bit
• Error Correction
• 2-10 Applications
• Chapter 3 Describing Logic Circuits
• 3-1 Boolean Constants and Variables
• 3-2 Truth Tables
• 3-3 OR Operation with OR Gates
• OR Gate
• Summary of the OR Operation
• 3-4 AND Operation with AND Gates
• AND Gate
• Summary of the AND Operation
• 3-5 NOT Operation
• NOT Circuit (INVERTER)
• Summary of Boolean Operations
• 3-6 Describing Logic Circuits Algebraically
• Operator Precedence
• Circuits Containing INVERTERs
• 3-7 Evaluating Logic-Circuit Outputs
• Analysis Using a Table
• 3-8 Implementing Circuits from Boolean Expressions
• 3-9 NOR Gates and NAND Gates
• NOR Gate
• NAND Gate
• 3-10 Boolean Theorems
• Multivariable Theorems
• 3-11 DeMorgan’s Theorems
• Implications of DeMorgan’s Theorems
• 3-12 Universality of NAND Gates and NOR Gates
• 3-13 Alternate Logic-Gate Representations
• Logic-Symbol Interpretation
• Summary
• 3-14 Which Gate Representation to Use
• Which Circuit Diagram Should Be Used?
• Bubble Placement
• Analyzing Circuits
• Asserted Levels
• Labeling Active-LOW Logic Signals
• Labeling Bistate Signals
• 3-15 Propagation Delay
• 3-16 Summary of Methods to Describe Logic Circuits
• 3-17 Description Languages Versus Programming Languages
• VHDL and AHDL
• Computer Programming Languages
• 3-18 Implementing Logic Circuits with PLDs
• 3-19 HDL Format and Syntax
• 3-20 Intermediate Signals
• Chapter 4 Combinational Logic Circuits
• 4-1 Sum-of-Products Form
• Product-of-Sums
• 4-2 Simplifying Logic Circuits
• 4-3 Algebraic Simplification
• 4-4 Designing Combinational Logic Circuits
• Complete Design Procedure
• 4-5 Karnaugh Map Method
• Karnaugh Map Format
• Looping
• Looping Groups of Two (Pairs)
• Looping Groups of Four (Quads)
• Looping Groups of Eight (Octets)
• Complete Simplification Process
• Filling a K Map from an Output Expression
• Don’t-Care Conditions
• Summary
• 4-6 Exclusive-OR and Exclusive-NOR Circuits
• Exclusive-OR
• Exclusive-NOR
• 4-7 Parity Generator and Checker
• 4-8 Enable/Disable Circuits
• 4-9 Basic Characteristics of Legacy Digital ICs
• Bipolar and Unipolar Digital ICs
• TTL Family
• CMOS Family
• Power and Ground
• Logic-Level Voltage Ranges
• Unconnected (Floating) Inputs
• Logic-Circuit Connection Diagrams
• 4-10 Troubleshooting Digital Systems
• 4-11 Internal Digital IC Faults
• Malfunction in Internal Circuitry
• Input Internally Shorted to Ground or Supply
• Output Internally Shorted to Ground or Supply
• Open-Circuited Input or Output
• Short Between Two Pins
• 4-12 External Faults
• Open Signal Lines
• Shorted Signal Lines
• Faulty Power Supply
• Output Loading
• 4-13 Troubleshooting Prototyped Circuits
• 4-14 Programmable Logic Devices
• PLD Hardware
• Programming a PLD
• Development Software
• Design and Development Process
• 4-15 Representing Data in HDL
• Bit Arrays/Bit Vectors
• Ahdl Bit Array Declarations
• 4-16 Truth Tables Using Hdl
• 4-17 Decision Control Structures in HDL
• IF/ELSE
• ELSIF
• Chapter 5 Flip-Flops and Related Devices
• 5-1 NAND Gate Latch
• Setting the Latch (FF)
• Resetting the Latch (FF)
• Simultaneous Setting and Resetting
• Summary of NAND Latch
• Alternate Representations
• Terminology
• 5-2 NOR Gate Latch
• Flip-Flop State on Power-Up
• 5-3 Troubleshooting Case Study
• 5-4 Digital Pulses
• 5-5 Clock Signals and Clocked Flip-Flops
• Clocked Flip-Flops
• Setup and Hold Times
• 5-6 Clocked S-R Flip-Flop
• Internal Circuitry of the Edge-Triggered S-R Flip-Flop
• 5-7 Clocked J-K Flip-Flop
• Internal Circuitry of the Edge-Triggered J-K Flip-Flop
• 5-8 Clocked D Flip-Flop
• Implementation of the D Flip-Flop
• Parallel Data Transfer
• 5-9 D Latch (Transparent Latch)
• 5-10 Asynchronous Inputs
• Designations for Asynchronous Inputs
• 5-11 Flip-Flop Timing Considerations
• Setup and Hold Times
• Propagation Delays
• Maximum Clocking Frequency, fMAX
• Clock Pulse HIGH and LOW Times
• Asynchronous Active Pulse Width
• Clock Transition Times
• 5-12 Potential Timing Problem in FF Circuits
• 5-13 Flip-Flop Applications
• 5-14 Flip-Flop Synchronization
• 5-15 Detecting an Input Sequence
• 5-16 Detecting a Transition or “Event”
• 5-17 Data Storage and Transfer
• Parallel Data Transfer
• 5-18 Serial Data Transfer: Shift Registers
• Hold Time Requirement
• Serial Transfer Between Registers
• Shift-Left Operation
• Parallel Versus Serial Transfer
• 5-19 Frequency Division and Counting
• Counting Operation
• State Transition Diagram
• MOD Number
• 5-20 Application of Flip-Flops with Timing Constraints
• Timing Issues
• 5-21 Microcomputer Application
• 5-22 Schmitt-Trigger Devices
• 5-23 One-Shot (Monostable Multivibrator)
• Nonretriggerable One-Shot
• Retriggerable One-Shot
• Actual Devices
• Monostable Multivibrator
• 5-24 Clock Generator Circuits
• Schmitt-Trigger Oscillator
• 555 Timer Used as an Astable Multivibrator
• Crystal-Controlled Clock Generators
• 5-25 Troubleshooting Flip-Flop Circuits
• Open Inputs
• Shorted Outputs
• Clock Skew
• 5-26 Sequential Circuits in PLDs Using Schematic Entry
• 5-27 Sequential Circuits Using HDL
• The D Latch
• 5-28 Edge-Triggered Devices
• 5-29 HDL Circuits with Multiple Components
• Chapter 6 Digital Arithmetic: Operations and Circuits
• 6-1 Binary Addition and Subtraction
• Binary Addition
• Binary Subtraction
• 6-2 Representing Signed Numbers
• 1’s-Complement Form
• 2’s-Complement Form
• Representing Signed Numbers Using 2’s Complement
• Sign Extension
• Negation
• Special Case in 2’s-Complement Representation
• 6-3 Addition in the 2’s-Complement System
• 6-4 Subtraction in the 2’s-Complement System
• Arithmetic Overflow
• Number Circles and Binary Arithmetic
• 6-5 Multiplication of Binary Numbers
• Multiplication in the 2’s-Complement System
• 6-6 Binary Division
• 6-7 BCD Addition
• Sum Equals 9 or Less
• Sum Greater than 9
• BCD Subtraction
• 6-8 Hexadecimal Arithmetic
• Hex Addition
• Hex Subtraction
• Hex Representation of Signed Numbers
• 6-9 Arithmetic Circuits
• Arithmetic/Logic Unit
• 6-10 Parallel Binary Adder
• 6-11 Design of a Full Adder
• K-Map Simplification
• Half Adder
• 6-12 Complete Parallel Adder with Registers
• Register Notation
• Sequence of Operations
• 6-13 Carry Propagation
• 6-14 Integrated-Circuit Parallel Adder
• Cascading Parallel Adders
• 6-15 2’s-Complement Circuits
• Addition
• Subtraction
• Combined Addition and Subtraction
• 6-16 ALU Integrated Circuits
• The 74LS382/74HC382 ALU
• Expanding the ALU
• Other ALUs
• 6-17 Troubleshooting Case Study
• 6-18 Using Altera Library Functions
• Megafunction LPMs for Arithmetic Circuits
• Using a Parallel Adder to Count
• 6-19 Logical Operations on Bit Arrays with HDLs
• 6-20 HDL Adders
• 6-21 Parameterizing the Bit Capacity of a Circuit
• Chapter 7 Counters and Registers
• 7-1 Asynchronous (Ripple) Counters
• Signal Flow
• MOD Number
• Frequency Division
• Duty Cycle
• 7-2 Propagation Delay in Ripple Counters
• 7-3 Synchronous (Parallel) Counters
• Circuit Operation
• Advantage of Synchronous Counters over Asynchronous
• Actual ICs
• 7-4 Counters with Mod Numbers <2N
• State Transition Diagram
• Displaying Counter States
• Changing the MOD Number
• General Procedure
• Decade Counters/BCD Counters
• 7-5 Synchronous Down and Up/Down Counters
• 7-6 Presettable Counters
• Synchronous Presetting
• 7-7 IC Synchronous Counters
• The 74ALS160-163/74HC160-163 Series
• The 74ALS190-191/74HC190-191 Series
• Multistage Arrangement
• 7-8 Decoding a Counter
• Active-HIGH Decoding
• Active-LOW Decoding
• BCD Counter Decoding
• 7-9 Analyzing Synchronous Counters
• 7-10 Synchronous Counter Design
• Basic Idea
• J-K Excitation Table
• Design Procedure
• Stepper Motor Control
• Synchronous Counter Design with D FF
• 7-11 Altera Library Functions for Counters
• 7-12 HDL Counters
• State Transition Description Methods
• Behavioral Description
• Simulation of Basic Counters
• Full-Featured Counters in HDL
• Simulation of Full-Featured Counter
• 7-13 Wiring HDL Modules Together
• MOD-100 BCD Counter
• 7-14 State Machines
• Simulation of State Machines
• Traffic Light Controller State Machine
• Choosing HDL Coding Techniques
• 7-15 Register Data Transfer
• 7-16 IC Registers
• Parallel In/Parallel Out—The 74ALS174/74HC174
• Serial In/Serial Out—The 74ALS166/74HC166
• Parallel In/Serial Out—The 74ALS165/74HC165
• Serial In/Parallel Out—The 74ALS164/74HC164
• 7-17 Shift-Register Counters
• Ring Counter
• Starting a Ring Counter
• Johnson Counter
• Decoding a Johnson Counter
• IC Shift-Register Counters
• 7-18 Troubleshooting
• 7-19 Megafunction Registers
• 7-20 HDL Registers
• 7-21 HDL Ring Counters
• 7-22 HDL One-Shots
• Nonretriggerable One-Shot Simulation
• Retriggerable, Edge-Triggered One-Shots in HDL
• Edge-Triggered Retriggerable One-Shot Simulation
• Chapter 8 Integrated-Circuit Logic Families
• 8-1 Digital IC Terminology
• Current and Voltage Parameters (See Figure 8-1)
• Fan-Out
• Propagation Delays
• Power Requirements
• Noise Immunity
• Invalid Voltage Levels
• Current-Sourcing and Current-Sinking Action
• IC Packages
• 8-2 The TTL Logic Family
• Circuit Operation—LOW State
• Circuit Operation—HIGH State
• Current-Sinking Action
• Current-Sourcing Action
• Totem-Pole Output Circuit
• TTL NOR Gate
• Summary
• 8-3 TTL Data Sheets
• Supply Voltage and Temperature Range
• Voltage Levels
• Maximum Voltage Ratings
• Power Dissipation
• Propagation Delays
• 8-4 TTL Series Characteristics
• Standard TTL, 74 Series
• Schottky TTL, 74S Series
• Low-Power Schottky TTL, 74LS Series (LS-TTL)
• Advanced Schottky TTL, 74AS Series (AS-TTL)
• Advanced Low-Power Schottky TTL, 74ALS Series
• 74F—Fast TTL
• Comparison of TTL Series Characteristics
• 8-5 TTL Loading and Fan-Out
• Determining the Fan-Out
• 8-6 Other TTL Characteristics
• Unconnected Inputs (Floating)
• Unused Inputs
• Tied-Together Inputs
• Biasing TTL Inputs Low
• Current Transients
• 8-7 MOS Technology
• The MOSFET
• Basic MOSFET Switch
• 8-8 Complementary MOS Logic
• CMOS Inverter
• CMOS NAND Gate
• CMOS NOR Gate
• CMOS SET-RESET FF
• 8-9 CMOS Series Characteristics
• 4000/14000 Series
• 74HC/HCT (High-Speed CMOS)
• 74AC/ACT (Advanced CMOS)
• 74AHC/AHCT (Advanced High-Speed CMOS)
• BiCMOS 5-V Logic
• Power-Supply Voltage
• Logic Voltage Levels
• Noise Margins
• Power Dissipation
• PD Increases with Frequency
• Fan-Out
• Switching Speed
• Unused Inputs
• Static Sensitivity
• Latch-Up
• 8-10 Low-Voltage Technology
• CMOS Family
• BiCMOS Family
• 8-11 Open-Collector/Open-Drain Outputs
• Open-Collector/Open-Drain Outputs
• Open-Collector/Open-Drain Buffer/Drivers
• IEEE/ANSI Symbol for Open-Collector/Drain Outputs
• 8-12 Tristate (Three-State) Logic Outputs
• Advantage of Tristate
• Tristate Buffers
• Tristate ICs
• IEEE/ANSI Symbol for Tristate Outputs
• 8-13 High-Speed Bus Interface Logic
• 8-14 CMOS Transmission Gate (Bilateral Switch)
• 8-15 IC Interfacing
• Interfacing 5-V TTL and CMOS
• CMOS Driving TTL
• CMOS Driving TTL in the HIGH State
• CMOS Driving TTL in the LOW State
• 8-16 Mixed-Voltage Interfacing
• Low-Voltage Outputs Driving High-Voltage Loads
• High-Voltage Outputs Driving Low-Voltage Loads
• 8-17 Analog Voltage Comparators
• 8-18 Troubleshooting
• Using a Logic Pulser and Probe to Test a Circuit
• Finding Shorted Nodes
• 8-19 Characteristics of an FPGA
• Power-Supply Voltage
• Logic Voltage Levels
• Power Dissipation
• Maximum Input Voltage and Output Current Ratings
• Switching Speed
• Chapter 9 MSI Logic Circuits
• 9-1 Decoders
• ENABLE Inputs
• BCD-to-Decimal Decoders
• BCD-to-Decimal Decoder/Driver
• Decoder Applications
• 9-2 BCD-to-7-Segment Decoder/Drivers
• Common-Anode Versus Common-Cathode LED Displays
• 9-3 Liquid-Crystal Displays
• Driving an LCD
• Types of LCDs
• 9-4 Encoders
• Priority Encoders
• 74147 Decimal-to-BCD Priority Encoder
• Switch Encoder
• 9-5 Troubleshooting
• 9-6 Multiplexers (Data Selectors)
• Basic Two-Input Multiplexer
• Eight-Input Multiplexer
• Four-Input Multiplexer
• Quad Two-Input MUX (74ALS157/HC157)
• 9-7 Multiplexer Applications
• Data Routing
• Parallel-to-Serial Conversion
• Operation Sequencing
• Logic Function Generation
• 9-8 Demultiplexers (Data Distributors)
• 1-Line-to-8-Line Demultiplexer
• Security Monitoring System
• Synchronous Data Transmission System
• Time Division Multiplexing
• 9-9 More Troubleshooting
• 9-10 Magnitude Comparator
• Data Inputs
• Outputs
• Cascading Inputs
• Applications
• 9-11 Code Converters
• Basic Idea
• Conversion Process
• Circuit Implementation
• Other Code Converter Implementations
• 9-12 Data Busing
• 9-13 The 74ALS173/HC173 Tristate Register
• 9-14 Data Bus Operation
• Data Transfer Operation
• Bus Signals
• Simplified Bus Timing Diagram
• Expanding the Bus
• Simplified Bus Representation
• Bidirectional Busing
• 9-15 Decoders Using HDL
• 9-16 The HDL 7-Segment Decoder/Driver
• 9-17 Encoders Using HDL
• 9-18 HDL Multiplexers and Demultiplexers
• 9-19 HDL Magnitude Comparators
• 9-20 HDL Code Converters
• Chapter 10 Digital System Projects Using HDL
• 10-1 Small-Project Management
• Definition
• Strategic Planning/Problem Decomposition
• Synthesis and Testing
• System Integration and Testing
• 10-2 Stepper Motor Driver Project
• Problem Definition
• Strategic Planning/Problem Decomposition
• Synthesis and Testing
• 10-3 Keypad Encoder Project
• Problem Analysis
• Strategic Planning/Problem Decomposition
• 10-4 Digital Clock Project
• Top-Down Hierarchical Design
• Building the Blocks from the Bottom Up
• MOD-12 Design
• Combining Blocks Graphically
• Combining Blocks Using Only HDL
• 10-5 Microwave Oven Project
• Definition of the Project
• Strategic Planning/Problem Decomposition
• Synthesis/Integration and Testing
• 10-6 Frequency Counter Project
• Chapter 11 Interfacing with the Analog World
• 11-1 Review of Digital Versus Analog
• 11-2 Digital-to-Analog Conversion
• Analog Output
• Input Weights
• Resolution (Step Size)
• Percentage Resolution
• What Does Resolution Mean?
• Bipolar DACs
• 11-3 DAC Circuitry
• Conversion Accuracy
• DAC with Current Output
• R/2R Ladder
• 11-4 DAC Specifications
• Resolution
• Accuracy
• Offset Error
• Settling Time
• Monotonicity
• 11-5 an Integrated-Circuit DAC
• 11-6 DAC Applications
• Control
• Automatic Testing
• Signal Reconstruction
• A/D Conversion
• Digital Amplitude Control
• Serial DACs
• 11-7 Troubleshooting DACs
• 11-8 Analog-to-Digital Conversion
• 11-9 Digital-Ramp ADC
• A/D Resolution and Accuracy
• Conversion Time, tC
• 11-10 Data Acquisition
• Reconstructing a Digitized Signal
• Aliasing
• Serial ADCs
• 11-11 Successive-Approximation ADC
• Conversion Time
• An Actual IC: The ADC0804 Successive-Approximation ADC
• 11-12 Flash ADCs
• Conversion Time
• 11-13 Other A/D Conversion Methods
• Dual-Slope Integrating ADC
• Voltage-to-Frequency ADC
• Sigma/Delta Modulation
• Pipelined ADC
• 11-14 Typical ADC Architectures for Applications
• 11-15 Sample-and-Hold Circuits
• 11-16 Multiplexing
• 11-17 Digital Signal Processing (DSP)
• Digital Filtering
• 11-18 Applications of Analog Interfacing
• Data Acquisition Systems
• Digital Camera
• Digital Cellular Telephone
• Chapter 12 Memory Devices
• 12-1 Memory Terminology
• 12-2 General Memory Operation
• Address Inputs
• The WE input
• Output enable (OE)
• Memory Enable
• 12-3 CPU–Memory Connections
• 12-4 Read-Only Memories
• ROM Block Diagram
• The Read Operation
• 12-5 ROM Architecture
• Output Buffers
• Register Array
• Address Decoders
• 12-6 ROM Timing
• 12-7 Types of ROMs
• Mask-Programmed ROM
• Programmable ROMs (PROMs)
• Erasable Programmable ROM (EPROM)
• Electrically Erasable PROM (EEPROM)
• 12-8 Flash Memory
• A Typical CMOS Flash Memory IC
• Flash Technology: NOR and NAND
• 12-9 ROM Applications
• Embedded Microcontroller Program Memory
• Data Transfer and Portability
• Bootstrap Memory
• Data Tables
• Data Converter
• Function Generator
• 12-10 Semiconductor RAM
• 12-11 RAM Architecture
• Read Operation
• Write Operation
• Chip Select
• Common Input/Output Pins
• 12-12 Static RAM (SRAM)
• Static-RAM Timing
• Read Cycle
• Write Cycle
• 12-13 Dynamic RAM (DRAM)
• 12-14 Dynamic RAM Structure and Operation
• Address Multiplexing
• 12-15 DRAM Read/Write Cycles
• DRAM Read Cycle
• DRAM Write Cycle
• 12-16 DRAM Refreshing
• 12-17 DRAM Technology
• Memory Modules
• FPM DRAM
• EDO DRAM
• SDRAM
• DDRSDRAM
• 12-18 Other Memory Technologies
• Magnetic Storage
• Optical Memory
• Phase Change Ram (PRAM)
• Ferroelectric RAM (FRAM)
• 12-19 Expanding Word Size and Capacity
• Expanding Word Size
• Expanding Capacity
• Incomplete Address Decoding
• Combining DRAM Chips
• 12-20 Special Memory Functions
• Cache Memory
• First-In, First-Out Memory (FIFO)
• Circular Buffers
• Chapter 13 Programmable Logic Device Architectures
• 13-1 Digital Systems Family Tree
• More on PLDs
• 13-2 Fundamentals of PLD Circuitry
• PLD Symbology
• 13-3 PLD Architectures
• PROMs
• Programmable Array Logic (PAL)
• Field Programmable Logic Array (FPLA)
• Generic Array Logic (GAL)
• 13-4 The Altera MAX and MAX II Families
• 13-5 Generations of HCPLDs
• Glossary
• Answers to Selected Problems
• index of ICs
• Index